SIVALLEY
Semiconductors
2018-05-28 16:43:15
₹300000
8-14 Yrs
Bengaluru
Senior DFT Lead (8+ Yrs of experience in DFT with 3+ Yrs in leading the SoC level DFT implementation) · Should have experience in leading the SoC level implementation (hierarchical) for Scan, MBIST, BSCAN insertion · Experience in Mentor Graphics tools/flows preferred TestKompress, Tessent/LV MBIST, Mentor TAP Generation · Understanding of EDT generation, implementation flow, OCC structure definitions for partitions and full-chip level and integration across · Interface between Design and PD and driving implementation as per Full-chip level DFT spec from the DFT architect on Scan, MBIST, BSCAN
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